Inphi Corporation, a high-speed analog semiconductor company, is the market leader in data transport and signal integrity solutions from fiber to memory. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center, and 40G/100G network environments. By leveraging our core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi went through a successful initial public offering in November 2010 and is publicly traded on NYSE under the symbol “IPHI.” Our innovative approaches have resulted in the company’s products being first to market in a number of key areas, including 40G/100G drivers and TiAs, as well as 100G Ethernet CMOS SERDES. We are seeking talented individuals to work on demanding technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
Inphi is seeking a Director of Design Engineering for DSP/Serdes Systems design Engineering. The Candidate must have a proven record of leading architecting and implementing advanced signal processing algorithms for physical layer chips preferably at speeds beyond 10G. The successful candidate must have a proven record of designing complex DSP PHY ICs and has successfully placed multiple products into volume production.
·Develop ASIC specification and micro-architecture of signal processing and communications algorithms
·High speed data path RTL implementation using Verilog, synthesis and backend
·Integrate vendor IP and support
·Well versed with the complete ASIC flow from micro-architecture to customer deployment
·Post-silicon debug and correlation
·Bachelors, Masters or PhD with minimum 10+ years of experience (or equivalent) in multi-million gates digital/mixed-signal IC design at 65, 40nm or smaller technology.
·Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
·Strong language user in Verilog, System Verilog, Perl, Unix Shell.
·Experience in both RTL and gate level verification and debug.
·Hands on experience with matching DSP block model functionality to RTL’s, synthesis, static timing analysis and functional verification
·Strong design experience in high speed DSP physical layer products
·Experience with chip bring up and functional validation of the product in the lab
·Strong system level modeling, debugging and troubleshooting
·Effective communication and presentation
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